1. Field of the Invention
The present invention relates to a field of processor control of memory and more specifically to providing staggered timing of control signals to control a plurality of memory devices.
2. Prior Art
Various schemes for accessing memory are well known in the prior art. In the simplest of structures, address lines and data lines are coupled to a memory, wherein address signals on the address lines access a given location of the memory for reading or writing of data. The data transfer is achieved on the data lines. Further, various control signals are coupled to the memory for providing timing and other functions, such as enabling the writing and/or reading operations associated with the memory.
Memory devices come in a variety of types and forms. One of the more well-known memory devices is a random-access-memory (RAM), which is fabricated as a semiconductor "chip". A RAM device is comprised of a plurality of memory locations called cells and these cells are structured into a matrix having rows and columns. The address signal must provide the row address and the column address to select a given cell location. In many instances row and column addresses are time multiplexed on the address lines and a row address strobe (RAS) and a column address strobe (CAS) are used to strobe in the row and column addresses, respectively, to the memory device.
In a typical prior art arrangement using a plurality of memory units, address and, data lines, the RAS and CAS lines are all coupled to the individual memory units. Generally, data transfer is achieved simultaneously from all or selective memory units. Various schemes are available for selective memory use, including the use of chip enable signals to enable the selected chip. In some instances, the plurality of memory units are arranged in an array.
One application of such use of a plurality of memories involves the utilization of a graphics processor to produce video images onto a display, such as a viewing screen. Generally, a processor is specially designated to perform as a graphics processor in manipulating video data to provide the image displayed. The memory is coupled to the graphics processor for the purpose of storing video data, which are to be used for providing pixel information to the display unit. For example, in a typical frame-buffer based graphics system, a digital representation of the image of a frame of the display is stored in the frame-buffer memory, wherein one or more bits of data represent each pixel of the viewing screen. An update processor renders a picture into the image memory and a display processor or a mapping circuit then reads the frame-buffer memory in raster scanned order to map the digital code to the protocol of the display screen, such as the red/green/blue (RGB) protocol. Because of the larger memory size requirement of the frame buffer, low cost dynamic random-access-memories (DRAMs) are normally used as the individual memory elements.
In systems where a single processor is used to perform the data manipulation function, the number of memory locations that can be updated each second, commonly referred to as the memory bandwidth, is typically the factor limiting the performance. Because of the use of common address, data and control lines to drive the memory, usually only one memory word is updated every memory cycle time, which is typically on the order of 300 nanoseconds for a DRAM. The memory bandwidth places a limitation on how quickly a new image can be drawn in the image memory.
It is appreciated then that what is needed is a scheme to increase the memory bandwidth of a graphics update processor without severely complicating the structure of a basic video system.